1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a fully differential simultaneous bi-directional (SBD) transceiver.
A claim of priority is made to Korean Patent Application No. 2003-55029, filed on Aug. 8, 2003, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated in its entirety by reference.
2. Description of the Related Art
Semiconductor devices such as processors, controllers, and memory devices generally include data transceivers for transmitting and receiving data. These transceivers typically transmit and/or receive data via one dedicated transmission line. Recently, semiconductor devices capable of simultaneously and bi-directionally transmitting and receiving data have been developed. Simultaneous bi-directional (hereinafter, referred to as ‘SBD’) transceivers are capable of simultaneously transmitting and receiving data during a single clock cycle via the single transmission line.
FIG. 1 generally illustrates an operative combination of two conventional SBD transceivers 10a and 10b connected via a transmission line forming a data transmission channel 16. SBD transceiver 10a includes a data driver 12a and a data receiver 14a. An internal data signal Dout1 to be transmitted is supplied to data driver 12a as an input data signal, and to data receiver 14a as a control signal. An output terminal associated with data driver 12a is connected to an input terminal associated with data receiver 14a. 
Data receiver 14a typically receives two reference voltages VrefH and VrefL that are used to compare signal levels. When the voltage level of internal data signal Dout1 ‘high (VH)’, data receiver 14a selects reference voltage VrefH, compares the level of the internal data signal Dout1 to the level of reference voltage VrefH, and outputs a data signal Din1 in accordance with the comparison result. When the level of internal data signal Dout1 is ‘low (VL)’, data receiver 14a selects reference voltage VrefL, compares the level of the internal data signal Dout1 to the level of reference voltage VrefL, and outputs data signal Din1 in accordance with the comparison result.
SBD transceiver 10b similarly includes a data driver 12b and a data receiver 14b. An internal data signal Dout2 to be transmitted is supplied to data driver 12b as an input data signal and to data receiver 14b as a control signal. An output terminal of data driver 12b is connected to an input terminal of data receiver 14b. 
Data receiver 14b operates in like fashion to data receiver 14a by respectively comparing the level of an internal data signal Dout2 to one of the two reference voltages VrefH and VrefL, and outputting a data output signal Din2 in accordance with the comparison.
FIG. 2 shows the relationship between selected input data signals and output data signals associated with the SBD transceivers 10a and 10b shown in FIG. 1. Referring to FIGS. 1 and 2, internal data signal Dout1 is ‘high (VH)’ during time periods T1, T2, and T5, and internal data signal Dout2 is ‘high (VH)’ during time periods T1, T3, and T5.
During T1, a voltage VCH apparent on data transmission channel 16 is high (VDDQ). Thus, data receiver 14a compares the voltage VCH on the channel 16 with reference voltage VrefH and outputs the output signal Din1 with a high level (VH). The data receiver 14b compares voltage VCH on channel 16 with reference voltage VrefH and outputs the output signal Din2 of a high level (VH).
During T2, voltage VCH on channel 16 is approximately Vmid. Vmid is a generally a voltage level half way between a supply voltage VDDQ and a ground voltage VSS. Thus, data receiver 14a compares voltage VCH on channel 16 with reference voltage VrefH and outputs the output signal Din1 of a low level (VL). Data receiver 14b compares voltage VCH on channel 16 with reference voltage VrefL and outputs the output signal Din2 of a high level (VH).
During T3, the voltage VCH on channel 16 is approximately Vmid. Thus, the data receiver 14a compares voltage VCH on channel 16 with reference voltage VrefL and outputs the output signal Din1 of a high level (VH). Data receiver 14b compares voltage VCH on channel 16 with reference voltage VrefH and outputs the output signal Din2 of a low level (VL).
The operation of SBD transceivers 10a and 10b during time periods T4 and T5 continues along this same line.
Each of the data drivers 12a and 12b swings between the supply voltage VDDQ and the ground voltage VSS, thus consuming considerable amounts of current. Further, since a swing voltage level for channel 16 must be half the supply voltage VDDQ, the respective sizes of data drivers 12a and 12b can become rather large. As a result, parasitic capacitances associated with the SBD transceivers 10a and 10b, as viewed from the perspective of data transmission channel 16, become significant. Indeed, the delay and signal distortion effects of these parasitic capacitances can impede the transmission of data between SBD transceivers 10a and 10b. This is particularly true as data transmission speeds increase.